Title :
Implementation of digital HDTV encoder with parallel sub-picture encoding modules and its joint bit-allocation strategy
Author :
Xiong, Hongkai ; Yu, Songyu ; Ye, Wei
Author_Institution :
Inst. of Image Commun. & Inf. Process., Shanghai Jiao Tong Univ., China
fDate :
11/1/2002 12:00:00 AM
Abstract :
Parallel processing is a feasible scheme for a digital HDTV encoder, to get round the dilemma in high-speed digital processing circuitry and real-time compression. This paper suggests an implementation procedure and a novel bit-allocation strategy for a digital high definition television (HDTV) encoder system with parallel processing architecture based on six horizontal strips division. Multiple sub-pictures encoding modules (SEMs) perform MPEG-2 coding respectively and simultaneously. Owing to the inherent deficiencies of MPEG-2 Test Model 5 (TM5) rate control scheme, how to allocate bit-rate among sub-pictures would become an inevitable challenge, which might behave with the coding quality to decrease worse and the buffer to underflow at scene changes, moreover give birth to non-consistent sub-pictures visual quality and dynamic quality variation in a composite HDTV frame on subjective and objective evaluation. We adapt a hierarchical joint optimized bit-allocation with sub-pictures´ average complexity measure and average bits per pixel in terms of their average quantization distortion, moreover incorporates scene detection to alleviate a possible worse sub-pictures quality inconsistency. In the paper, we describe an elaborate procedure including general framework, sub-pictures division module, sub-picture encoding module and sub-pictures synthesis module, then deduce the joint bit-allocation strategy for sub-pictures encoding and the auxiliary rate adaptive procedure for scene changes. Experimental results demonstrate that our proposed scheme not only alleviates the boundary effect, but also promises the sub-pictures quality consistency. The proposed scheme might be devoted to the multiprogram broadcast application and the multiple access sceneries.
Keywords :
digital television; high definition television; parallel architectures; video codecs; MPEG-2 Test Model 5; MPEG-2 coding; TM5 rate control scheme; auxiliary rate adaptive procedure; average quantization distortion; bit-allocation strategy; buffer; coding quality; digital HDTV encoder; hierarchical joint optimized bit allocation; high definition television; high-speed digital processing circuitry; horizontal strips-division; multiple access sceneries; multiple sub-pictures encoding modules; multiprogram broadcast application; parallel processing architecture; real-time compression; scene detection; sub-picture encoding module; sub-pictures division module; sub-pictures quality; sub-pictures synthesis module; Circuits; Distortion measurement; Encoding; HDTV; Layout; Parallel processing; Strips; TV; Testing; Transform coding;
Journal_Title :
Consumer Electronics, IEEE Transactions on
DOI :
10.1109/TCE.2003.1196418