DocumentCode :
1190043
Title :
An Algorithm for Synthesis of Multiple-Output Combinational Logic
Author :
Schneider, Peter R. ; Dietmeyer, Donald L.
Author_Institution :
IEEE
Issue :
2
fYear :
1968
Firstpage :
117
Lastpage :
128
Abstract :
Abstract—A computer-oriented algorithm for synthesizing combinational logic circuits from a collection of functionally packaged circuits is developed. The algorithm uses a hierarchy of "goals" in an iterative decision process in a manner similar to that employed by theorem proving and gamne playing programs. With each iteration a set of "tasks" finds the circuit package which satisfies the highest level goal while meeting circuit constraints.
Keywords :
Index terms—Circuit constraints, combinational logic synthesis, decomposition, design algorithm, design goals, logic design automation, module library.; Algorithm design and analysis; Circuit synthesis; Combinational circuits; Costs; Digital systems; Iterative algorithms; Logic circuits; Logic design; Logic functions; Packaging; Index terms—Circuit constraints, combinational logic synthesis, decomposition, design algorithm, design goals, logic design automation, module library.;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/TC.1968.227399
Filename :
1687301
Link To Document :
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