Title :
Unitary Shift-Register Realizations of Sequential Machines
Author :
Su, C.C. ; Yau, S.S.
Author_Institution :
IEEE
fDate :
4/1/1968 12:00:00 AM
Abstract :
Abstract—The problem of determining secondary state assignments for sequential machines such that the binary memory elements are connected in the form of shift registers is studied. An algorithm for finding such state assignments is developed. One or more code words may be assigned to a state of the sequential machine. The only restriction is that the realizations be unitary. A single shift-register realization of a sequential machine is unitary if and only if all the code words assigned to a state have the same first digits. A multiple shift-register realization of a sequential machine is unitary if and only if all the code words assigned to a state have l identical digits, where l is the number of shift registers in the realization. With our technique, the unitary realizations with the minimum number of shift registers can be obtained for any finite, deterministic, synchronous, and reduced (minimal-state) sequential machine, each of whose states has a nonempty predecessor set. The algorithm is suitable for programming on digital computers.
Keywords :
Index terms—Algorithms, many-to-one state assignments, se-quential machines, shift-register realizations, unitary coding.; Circuit faults; Control systems; Laboratories; Logic circuits; Military computing; Read only memory; Sequential circuits; Shift registers; Switching circuits; Index terms—Algorithms, many-to-one state assignments, se-quential machines, shift-register realizations, unitary coding.;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.1968.229383