A parallel bit-level maximum/minimum selector for digital and video signal processing

Author

Lee, Chen-Yi ; Juan, Shih-Chou ; Yang, Wen-Wei

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

Volume

41

Issue

10

fYear

1994

fDate

10/1/1994 12:00:00 AM

Firstpage

693

Lastpage

695

Abstract

This paper presents a novel circuit for parallel bit-level maximum/minimum selection. The selection is based on a label-updating scheme which sequentially scans a set of data patterns from MSB to LSB and generates corresponding labels. The complete circuit realizing this scheme consists of a set of updating units and a global OR unit, where each updating unit is composed of only a few basic gates. Due to structure modularity, the developed circuit provides a very cost-effective hardware solution for comparing large volumes of data patterns as those required in digital and video signal processing

Keywords

application specific integrated circuits; digital signal processing chips; parallel architectures; DSP architecture; data patterns; digital signal processing; global OR unit; label-updating scheme; parallel bit-level maximum/minimum selector; structure modularity; video signal processing; Application specific integrated circuits; Circuit synthesis; Councils; Decision making; Digital signal processing; Hardware; Signal processing algorithms; System-on-a-chip; Timing; Video signal processing;

fLanguage

English

Journal_Title

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

1057-7130

Type

jour

DOI

10.1109/82.329739

Filename

329739