DocumentCode :
1190985
Title :
Partition-and-shift LDPC codes
Author :
Lu, Jin ; Moura, José M F
Author_Institution :
Sun Microsystems, Lafayette, CO, USA
Volume :
41
Issue :
10
fYear :
2005
Firstpage :
2977
Lastpage :
2979
Abstract :
This paper describes a new type of regular structured low-density parity-check (LDPC) code: the partition-and-shift LDPC (PS-LDPC) code. PS-LDPC codes can be easily designed to have large girth. The code construction is simple to explain: we divide the bit and check nodes in the Tanner graph into subsets and connect nodes in these subsets according to a set of parameters called shifts. We derive a general theorem on the shifts to prevent cycles that are harmful to LDPC decoding. This theorem provides a methodology to design PS-LDPC codes with arbitrary column weight j and large girth g. Simulation results over EPR4 channels demonstrate the good bit-error rate performance of PS-LDPC codes.
Keywords :
decoding; error correction codes; magnetic recording; parity check codes; EPR4 channel; LDPC decoding; PS-LDPC code; Tanner graph; bit node; bit-error rate performance; check node; code construction; error floor; low-density parity-check code; Bipartite graph; Bit error rate; Design methodology; Floors; Iterative decoding; Magnetic recording; Parity check codes; Sum product algorithm; Sun; USA Councils; Error floor; girth; low-density parity-check (LDPC);
fLanguage :
English
Journal_Title :
Magnetics, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9464
Type :
jour
DOI :
10.1109/TMAG.2005.854446
Filename :
1519179
Link To Document :
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