An improved bit-flipping scheme to achieve run length control in coded systems

Author

Li, Zongwang ; Xie, Jin ; Kumar, B. V K Vijaya

Author_Institution

Data Storage Syst. Center, Carnegie Mellon Univ., Pittsburgh, PA, USA

Volume

41

Issue

10

fYear

2005

Firstpage

2980

Lastpage

2982

Abstract

We propose an improved bit-flipping scheme that combines error-correcting codes such as low-density parity check codes with run length limit (RLL) constraints. In addition to its compatibility with soft decision decoding, the proposed scheme has the advantages of no error propagation and fixed block length. Testing with simulated data and real data show good performance. The loss in performance due to the introduction of RLL constraint is less than 0.1 dB at bit-error rate 10^-6 and block-error rate 10^-4.

Keywords

error correction codes; iterative decoding; parity check codes; RLL constraint; bit-error rate; bit-flipping scheme; block-error rate; coded system; error-correcting code; iterative detection; low-density parity check code; run length control; run length limit; soft decision decoding; Bit error rate; Control systems; Data storage systems; Decoding; Encoding; Error correction codes; Parity check codes; Performance loss; Testing; USA Councils; Iterative detection; low-density parity check (LDPC) codes; run length limit;

fLanguage

English

Journal_Title

Magnetics, IEEE Transactions on

Publisher

ieee

ISSN

0018-9464

Type

jour

DOI

10.1109/TMAG.2005.854457

Filename

1519180