DocumentCode :
1191166
Title :
New global routing subsystem for CMOS gate arrays
Author :
Lu, A. ; Wu, X. ; Zhuang, W. ; Chen, W.K.
Author_Institution :
Nanjing Inst. of Post & Telecommun., China
Volume :
141
Issue :
5
fYear :
1994
fDate :
10/1/1994 12:00:00 AM
Firstpage :
421
Lastpage :
426
Abstract :
A new global routing subsystem, the `LSIS-II Layout System´ for CMOS gate array, is presented. This subsystem consists of three new algorithms, the main purpose of which is to assign available resources evenly. The first two algorithms, called EOFCW and EOFCC, show how to arrange nets so that horizontal resources are used evenly; the third algorithm PACR helps the channel router to utilise vertical resources in the channel reasonably by reassigning some pins in the contact region and thereby eliminate the bottle-necks of the horizontal resources. The present algorithm is different from those existing because it adjusts nets by analysing usable resources and the features of nets. Moreover, using the soft interface concept of system design, this subsystem considers not only the characteristics of the placement and initial global routing but also the requirement of a detailed routing for resources. The subsystem has been implemented on Micro VAX-II. Experimental results verify that the subsystem is quite efficient
Keywords :
CMOS integrated circuits; circuit layout CAD; logic CAD; logic arrays; network routing; CMOS gate arrays; EOFCC; EOFCW; LSIS-II Layout System; Micro VAX-II; PACR; algorithms; contact region; global routing subsystem; nets; pin assignment; resource assignment; soft interface; system design;
fLanguage :
English
Journal_Title :
Circuits, Devices and Systems, IEE Proceedings -
Publisher :
iet
ISSN :
1350-2409
Type :
jour
DOI :
10.1049/ip-cds:19941315
Filename :
329863
Link To Document :
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