• DocumentCode
    1191285
  • Title

    Fast VLSI architectures using nonredundant multibit recoding for computing AY mod N

  • Author

    Prasanna, B.S. ; Mohan, P. V Ananda

  • Author_Institution
    Arcus Technol. Ltd., Bangalore, India
  • Volume
    141
  • Issue
    5
  • fYear
    1994
  • fDate
    10/1/1994 12:00:00 AM
  • Firstpage
    345
  • Lastpage
    349
  • Abstract
    A recently proposed technique for multiplication using two-bit recoding, which does not require subtraction operations, is extended for fast AB mod N evaluation. Architectures considering 2, 4, 8 and 16 bit recoding are considered and compared regarding the ALU complexity and speed requirements
  • Keywords
    VLSI; computational complexity; computer architecture; digital arithmetic; digital signal processing chips; ALU complexity; VLSI architecture; multiplication; nonredundant multibit recoding; speed requirements; two-bit recoding;
  • fLanguage
    English
  • Journal_Title
    Circuits, Devices and Systems, IEE Proceedings -
  • Publisher
    iet
  • ISSN
    1350-2409
  • Type

    jour

  • DOI
    10.1049/ip-cds:19941166
  • Filename
    329883
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1191285