DocumentCode :
1191292
Title :
A hybrid floating-point logarithmic number system processor
Author :
Taylor, Fred J.
Volume :
32
Issue :
1
fYear :
1985
fDate :
1/1/1985 12:00:00 AM
Firstpage :
92
Lastpage :
95
Abstract :
The attributes of the traditional floating-point processor and the logarithmic number system are combined. The result is a hybrid system which offers some advantages over the familiar floating-point system. The new system, called the 
, does not require exponent alignment during addition, supports high-speed addition and multiplication, has an efficient accumulator structure, and admits a simple VLSI realization.
, does not require exponent alignment during addition, supports high-speed addition and multiplication, has an efficient accumulator structure, and admits a simple VLSI realization.Keywords :
Floating-point arithmetic; Logarithmic arithmetic; Acoustic signal processing; Circuit noise; Digital filters; Dynamic range; Hardware; Narrowband; Noise shaping; Speech processing; State-space methods; Very large scale integration;
fLanguage :
English
Journal_Title :
Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0098-4094
Type :
jour
DOI :
10.1109/TCS.1985.1085588
Filename :
1085588
Link To Document :
