Direct Measurement of Top and Sidewall Interface Trap Density in SOI FinFETs

Conventional charge pumping is demonstrated on triple-gate silicon-on-insulator FinFET gated-diode structures with varying fin widths. A simple technique is proposed and verified allowing to independently estimate fin top and sidewall interface trap density. A higher interface state density on the sidewalls is observed, which is attributed to higher fin sidewall roughness. The methodology is also demonstrated to be sensitive to fin sidewall surface crystallographic orientation. The technique presents a straightforward means of assessing the fin sidewall and topwall interface quality, which can then be directly correlated with both processing influences and reliability effects