DocumentCode :
1191510
Title :
Impact of High- 
Offset Spacer in 65-nm Node SOI Devices
Author :
Ma, Ming-Wen ; Wu, Chien-Hung ; Yang, Tsung-Yu ; Kao, Kuo-Hsing ; Wu, Woei-Cherng ; Wang, Shui-Jinn ; Chao, Tien-Sheng ; Lei, Tan-Fu
Author_Institution :
Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu
Volume :
28
Issue :
3
fYear :
2007
fDate :
3/1/2007 12:00:00 AM
Firstpage :
238
Lastpage :
241
Abstract :
In this letter, 65-nm node silicon-on-insulator devices with high-kappa offset spacer dielectric were investigated by extensive 2-D device simulation. The result shows that the high-kappa offset spacer dielectric can effectively increase the on-state driving current ION and reduce the off leakage current IOFF due to the high vertical fringing electric field effect. This fringing field can significantly improve the ION/IOFF current ratio and the subthreshold swing compared with the conventional oxide spacer. Consequently, the gate-to-channel control ability is enhanced by the fringing field via the high-kappa offset spacer dielectric
Keywords :
electric field effects; leakage currents; semiconductor device testing; silicon-on-insulator; 2D device simulation; 65 nm; SOI devices; driving current; fringing electric field effect; fringing field; gate-to-channel control; high-k offset spacer dielectric; leakage current; oxide spacer; silicon-on-insulator; subthreshold swing; CMOS technology; Circuits; Dielectrics; Electric resistance; Immune system; Leakage current; MOSFETs; Medical simulation; Silicon on insulator technology; Space technology; Fringing electric field; high-$kappa$
fLanguage :
English
Journal_Title :
Electron Device Letters, IEEE
Publisher :
ieee
ISSN :
0741-3106
Type :
jour
DOI :
10.1109/LED.2007.891282
Filename :
4114575
Link To Document :
