R68-37 Intercommunication of Processors and Memory

The purpose of this paper is to explore the effect of multiple modules of memory together with multiple bus lines for providing effective communication between memory and processors or channel controllers. Apparently the study was undertaken to determine an optimum configuration of equipment for an installation to be made by a computer manufacturer to a university. It suffers from the necessary evil which abides in studying a particular system under specific limitations applying to that system. The author has made no attempt to generalize his results regarding priority and processor performance as effected by the number of modules and buses available. The special restrictions which apply are in terms of channel controller timing and drum unit datum acquisition.