A possible scaling limit for enhancement-mode GaAs MESFETs in DCFL circuits

Author

Hirose, Mayumi ; Uchitomi, Naotaka

Author_Institution

Toshiba Corp., Kawasaki, Japan

Volume

39

Issue

12

fYear

1992

fDate

12/1/1992 12:00:00 AM

Firstpage

2681

Lastpage

2685

Abstract

A possible scaling limit for ion-implanted GaAs MESFETs with buried p-layer LDD structure has been numerically investigated. A Schottky-contact model with a thin interfacial layer and interface states was used to simulate the Schottky-barrier height of a scaled-down MESFETs. When enhancement-mode MESFETs in direct-coupled FET logic (DCFL) circuits are scaled down, the gate length can be reduced to 0.21 μm at an interface-state density of 6.6×10¹² cm^-2·eV^-1, when the barrier height is greater than 0.6 V, the threshold voltage is less than 0.1 V, and the channel aspect ratio is 8

Keywords

III-V semiconductors; Schottky gate field effect transistors; direct coupled FET logic; field effect integrated circuits; gallium arsenide; integrated logic circuits; semiconductor device models; DCFL circuits; GaAs; MESFETs; Schottky-contact model; buried p-layer LDD structure; channel aspect ratio; direct-coupled FET logic; enhancement-mode; interface-state density; ion-implanted; logic IC; monolithic IC; scaling limit; threshold voltage; Circuit simulation; FETs; Gallium arsenide; Interface states; Large scale integration; Logic circuits; MESFET circuits; Numerical models; Poisson equations; Threshold voltage;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.168747

Filename

168747