DocumentCode :
1191761
Title :
A Low-Dropout Regulator for SoC With 
-Reduction
Author :
Lau, Sai Kit ; Mok, Philip K T ; Leung, Ka Nang
Author_Institution :
Dept. of Electron. & Comput. Eng., Hong Kong Univ. of Sci. & Technol., Hong Kong, China
Volume :
42
Issue :
3
fYear :
2007
fDate :
3/1/2007 12:00:00 AM
Firstpage :
658
Lastpage :
664
Abstract :
A low-dropout regulator for SoC, with an advanced Q-reduction circuit to minimize both the on-chip capacitance and the minimum output-current requirement down to 100 muA, is introduced in this paper. The idea has been implemented in a standard 0.35-mum CMOS technology (VTHN ap 0.55 V and |VTHP| ap 0.75 V). The required on-chip capacitance is reduced to 6 pF, comparing to 25 pF for the case without Q-reduction circuit. From the experimental results, the proposed regulator-circuit implementation enables voltage regulation down to a 1.2-V supply voltage, and a dropout voltage of 200 mV at 100-mA maximum output current.
Keywords :
CMOS integrated circuits; Q-factor; capacitance; system-on-chip; voltage regulators; 0.35 micron; 0.55 V; 0.75 V; 1.2 V; 100 mA; 100 muA; 200 mV; 25 pF; 6 pF; CMOS technology; Q-reduction circuit; SoC; low-dropout regulator; on-chip capacitance; power management; voltage regulation; CMOS technology; Capacitance; Capacitors; Circuits; Energy management; Frequency; Power system management; Regulators; System-on-a-chip; Voltage control; $Q$
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.2006.891496
Filename :
4114753
Link To Document :
