A 0.5-V 74-dB SNDR 25-kHz Continuous-Time Delta-Sigma Modulator With a Return-to-Open DAC

Author

Pun, Kong-Pang ; Chatterjee, Shouri ; Kinget, Peter R.

Author_Institution

Dept. of Electron. Eng., Chinese Univ. of Hong Kong, Hong Kong, China

Volume

42

Issue

3

fYear

2007

fDate

3/1/2007 12:00:00 AM

Firstpage

496

Lastpage

507

Abstract

A 0.5-V third-order one-bit fully-differential continuous-time DeltaSigma modulator is presented. The presented modulator architecture uses true low-voltage design techniques, and does not require internal voltage boosting or low-threshold devices. A return-to-open architecture that enables the ultra-low-voltage realization of return-to-zero signaling for the feedback DAC is proposed. The ultra-low-voltage operation is further enabled by a body-input gate-clocked comparator, and body-input operational transconductance amplifiers for the active-RC loop filter. Fabricated on a 0.18-mum CMOS process, the modulator achieves a peak SNDR of 74 dB in a 25 kHz bandwidth, and occupies an area of 0.6 mm²; the modulator core consumes 300 muW.

Keywords

CMOS integrated circuits; comparators (circuits); delta-sigma modulation; low-power electronics; 0.18 micron; 0.5 V; 25 kHz; 300 muW; active-RC loop filter; body-input circuit; continuous-time delta-sigma modulator; fully-differential modulator; low-voltage design; return-to-open DAC; return-to-zero signaling; third-order modulator; Analog circuits; Bandwidth; Boosting; CMOS technology; Delta modulation; Feedback; Filters; Low voltage; Operational amplifiers; Transconductance; Body-input circuit; continuous-time delta-sigma modulator; return-to-zero signaling; ultra-low-voltage circuit;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2006.891716

Filename

4114760