DocumentCode :
1192275
Title :
Low programming voltage floating gate analogue memory cells in standard VLSI CMOS technology
Author :
Durfee, D.A. ; Shoucair, F.S.
Author_Institution :
Brown Univ., Providence, RI, USA
Volume :
28
Issue :
10
fYear :
1992
fDate :
5/7/1992 12:00:00 AM
Firstpage :
925
Lastpage :
927
Abstract :
Floating gate MOSFET structures were fabricated in a standard 2 mu m double-polysilicon CMOS process which requires programming voltages of only 6.5-9 V. This considerable reduction in programming voltage is achieved by simultaneously exploiting tunnelling through the interpolysilicon oxide and capacitive geometries whose top poly-layers overlap the edges of the lower poly-layers.
Keywords :
CMOS integrated circuits; VLSI; analogue storage; 2 micron; 6.5 to 9 V; VLSI CMOS technology; analogue memory cells; capacitive geometries; double-polysilicon CMOS process; floating gate; interpolysilicon oxide; programming voltages; tunnelling;
fLanguage :
English
Journal_Title :
Electronics Letters
Publisher :
iet
ISSN :
0013-5194
Type :
jour
DOI :
10.1049/el:19920586
Filename :
137193
Link To Document :
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