Title :
Low programming voltage floating gate analogue memory cells in standard VLSI CMOS technology
Author :
Durfee, D.A. ; Shoucair, F.S.
Author_Institution :
Brown Univ., Providence, RI, USA
fDate :
5/7/1992 12:00:00 AM
Abstract :
Floating gate MOSFET structures were fabricated in a standard 2 mu m double-polysilicon CMOS process which requires programming voltages of only 6.5-9 V. This considerable reduction in programming voltage is achieved by simultaneously exploiting tunnelling through the interpolysilicon oxide and capacitive geometries whose top poly-layers overlap the edges of the lower poly-layers.
Keywords :
CMOS integrated circuits; VLSI; analogue storage; 2 micron; 6.5 to 9 V; VLSI CMOS technology; analogue memory cells; capacitive geometries; double-polysilicon CMOS process; floating gate; interpolysilicon oxide; programming voltages; tunnelling;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19920586