Investigation Into the Scalability of Selectively Implanted Buried Subcollector (SIBS) for Submicrometer InP DHBTs

Recent attempts to achieve 400 GHz or higher f_T and f _MAX with InP heterojunction bipolar transistors (HBTs) have resulted in aggressive scaling into the deep submicrometer regime. In order to alleviate some of the traditional mesa scaling rules, several groups have explored selectively implanted buried subcollectors (SIBS) as a means to decouple the intrinsic and extrinsic collector design. This allows tau_C to be minimized without incurring a large total C_BC increase, and hence, a net improvement in f_T and f_MAX is achieved. This paper represents the first investigation into the series resistance and capacitance characteristics of submicrometer-width SIBS regions (as narrow as 350 nm) for InP double HBTs. Although the SIBS resistance is higher than that of epitaxially grown layers, the SIBS concept is able to provide good dopant activation and a significant decrease in C_BC. S-parameter measurements are presented to clarify the impact of SIBS geometry variations, caused by both intentional device design and process variations, on f_T and f_MAX. Parasitic resistances and high background doping limit the f_T improvement, but the C_BC reduction is sufficient to demonstrate a 30% increase in f_MAX. Results indicate that further improvements in f_T and f_MAX using the SIBS concept will be possible