A non-exact-multiplication scheme for digital filter implementation using bit-slice components

In the implementation of digital filters using bit-slice components, a significant amount of hardware can be saved with insignificant loss of performance if the multiplications involving the least significant bits of the signal and coefficient values are ignored. The effect is the introduction of an error noise source in the multiplier. Optimum hardware count for a given total output noise power is achieved when the noise power arises from ignoring the product of the least significant bits equals the noise power due to arithmetic rounding.