Modeling and Characterization of Effects of Dummy-Gate Bias on LDMOSFETs

The bias effects of dummy gate on drain current, resistance, capacitance, quasi-saturation, and breakdown of Si laterally diffused MOSFET transistor (LDMOSFET) are modeled and characterized. Two-dimensional numerical simulations are used to explain experimental data, as well as to extract functional dependence of the drain-end channel potential on dummy-gate bias. The results are incorporated into the first five-terminal LDMOSFET model that accounts for dummy-gate bias. The model is a modification of the Berkeley Short-channel IGFET Model 4 and is implemented in the Verilog-A code. The model is validated by measured currents, capacitances, small- and large-signal radio-frequency (RF) performances under different biases. The model correctly predicts that positive dummy-gate bias can improve the maximum RF power, efficiency, and linearity of the LDMOSFET. These results suggest adaptive dummy-gate bias as a convenient alternative to adaptive drain bias in envelope-tracking linearity and efficiency-enhancement of LDMOSFET-based RF power amplifiers