Design and implementation of cascaded switched-capacitor delay equalizers

The purpose of this paper is to present design techniques for the realization of switched-capacitor (SC) delay equalizers. The first portion of the paper addresses the limitations associated with the design of a single biquadratic all-pass section. It is shown that the conflicting requirements of limiting the total capacitor area and achieving low sensitivity can usually be adequately reconciled. Next the design of multistage delay equalizers is investigated. A "staggering" technique is presented for significantly reducing op amp settling effects in cascaded stages and it is shown how this may be implemented in a parasitic-insensitive fashion. Examples which illustrate the various design procedures are given.