A new method for detecting the polysilicon gate reentrant of the submicron LDD MOSFET´s

With the continued shrinkage of the CMOS devices to the deep submicron regime, the control of the gate-to-drain overlap is becoming a stringent problem. We report that the gate-to-drain (source) current of an LDD p-MOSFET under a high positive gate-to-drain (source) bias is strongly correlated to the oxide thickness in the polysilicon gate edge and, consequently, to the gate-to-drain overlap capacitance. A simple physical model is then constructed to explain the observed correlation. Monitoring the poly gate reentrant by measuring the gate-to-drain current is simple and can be easily implemented in the parametric electrical tests in a process line