A novel approach for power reduction in asynchronous circuits by using AFPT

In this paper, a novel approach for power reduction in asynchronous circuits by using Asynchronous Fine-Grain Power-Gated Technique (AFPT) introduced. An AFPT developed by Improved Efficient Charge Recovery Logic (IECRL), which gives logic function to the next succeeding stage. In the AFPT circuit, IECRL gates attains power from hand shake controller and become active only when executing required calculations. In active mode the leakage currents are reduced by providing high resistance path through the NMOS transistor in pull-up network. In inactive mode IECRL gates are not taken any amount of power, this gives insignificant leakage power dissipation. Its maximum power saving against ECRL is up to 89.35%. In AFPT circuit handshake controller used to provide power to the IECRL gate and which handles the hand shaking with the neighboring stages. In the AFPT circuit PCR mechanism is used to transfer the charge of discharging phase of IECRL gate to evaluate phase of the another IECRL gate, to reduce the energy dissipation. Early discharging of IECRL gate can be achieved by using modified C-element called C*-element.