A quantitative methodology for rapid prototyping and high-level synthesis of signal processing algorithms

The paper introduces a systematic quantitative methodology to prototype deterministic recursive DSP algorithms onto multiple programmable signal processors. A scheduling framework that is based upon linear integer programming techniques is used to obtain rate, processor, delay, and communications optimal schedules for a given data flow graph representation of a signal processing algorithm. This powerful design synthesis environment facilitates optimal scheduling for randomly connected heterogeneous systems with multiple pipelined functional units and finite resources in VLSI. This framework can also be used in the high-level synthesis of efficient register-transfer level (RTL) VLSI descriptions from behavioral specifications