A quantitative methodology for rapid prototyping and high-level synthesis of signal processing algorithms

Author

Madisetti, Vijay K. ; Curtis, Bryce A.

Author_Institution

Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA

Volume

42

Issue

11

fYear

1994

fDate

11/1/1994 12:00:00 AM

Firstpage

3188

Lastpage

3208

Abstract

The paper introduces a systematic quantitative methodology to prototype deterministic recursive DSP algorithms onto multiple programmable signal processors. A scheduling framework that is based upon linear integer programming techniques is used to obtain rate, processor, delay, and communications optimal schedules for a given data flow graph representation of a signal processing algorithm. This powerful design synthesis environment facilitates optimal scheduling for randomly connected heterogeneous systems with multiple pipelined functional units and finite resources in VLSI. This framework can also be used in the high-level synthesis of efficient register-transfer level (RTL) VLSI descriptions from behavioral specifications

Keywords

VLSI; integer programming; linear programming; scheduling; signal processing; software prototyping; VLSI; behavioral specifications; communications optimal schedules; data flow graph representation; delay; deterministic recursive DSP algorithms; finite resources; functional units; high-level synthesis; linear integer programming; multiple programmable signal processors; optimal scheduling; quantitative methodology; randomly connected heterogeneous systems; rapid prototyping; register-transfer level; scheduling framework; signal processing algorithms; Delay; Digital signal processing; Flow graphs; Linear programming; Optimal scheduling; Processor scheduling; Prototypes; Signal processing; Signal processing algorithms; Very large scale integration;

fLanguage

English

Journal_Title

Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

1053-587X

Type

jour

DOI

10.1109/78.330377

Filename

330377