Time-domain sensitivity analysis of dynamic sense amplifier of an n-MOS dynamic RAM

The time-domain sensitivity analysis of a dynamic sense amplifier (DSA) is presented, based on an adjoint system solution. An admissible range of parameter variations for correct latching is computed from the sensitivity analysis. It has been shown that the sense amplifier sensitivity to the load capacitance and the gate to source capacitances of the latching transistors is dependent on the slope of the latching signal. It has also been shown that for a perfectly balanced sense amplifier there exists an optimal slope of the latching signal for which the sense amplifier performance is insensitive to the variations in gate to source capacitances.