Title :
Improved domino logic for high speed design
Author :
Jia, Song ; Liu, Fei ; Ji, Lijiu
Author_Institution :
Inst. of Microelectron., Peking Univ., Beijing, China
fDate :
4/17/2003 12:00:00 AM
Abstract :
Techniques are introduced to improve the speed of domino logic. With an inverted clock scheme, a serial transistor is removed and capacitances at the output node are reduced in the new structures. HSPICE simulation shows that over 20% performance enhancement is achieved.
Keywords :
CMOS logic circuits; capacitance; high-speed integrated circuits; integrated circuit design; logic design; timing; CMOS logic style; domino logic; high performance design; high speed design; inverted clock scheme; output node capacitance reduction;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20030422
