DocumentCode :
1193760
Title :
Analog Automatic Test Pattern Generation for Quasi-Static Structural Test
Author :
Zjajo, Amir ; De Gyvez, José Pineda
Author_Institution :
NXP Semicond., Eindhoven, Netherlands
Volume :
17
Issue :
10
fYear :
2009
Firstpage :
1383
Lastpage :
1391
Abstract :
A new approach for structural, fault-oriented analog test generation methodology to test for the presence of manufacturing-related defects is proposed. The output of the test generator consists of optimized test stimuli, fault coverage and sampling instants that are sufficient to detect the failure modes in the circuit under test. The tests are generated and evaluated on a multistep ADC taking into account the potential fault masking effects of process spread on the faulty circuit responses. Similarly, the test generator results offer indication for the circuit partitioning within the framework of circuit performance, area and testability.
Keywords :
analogue circuits; automatic test pattern generation; analog automatic test pattern generation; circuit partitioning; fault-oriented analog test generation; multistep ADC; quasi-static structural test; Analog ATPG; analog test; parametric fault model; structural test;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/TVLSI.2008.2003517
Filename :
4801592
Link To Document :
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