Title :
Design of efficient modulo 2n + 1 multipliers
Author :
Vergos, H.T. ; Efstathiou, C.
Author_Institution :
Comput. Eng. & Informatics Dept., Univ. of Patras
fDate :
1/1/2007 12:00:00 AM
Abstract :
A new modulo 2n+1 multiplier architecture is proposed for operands in the weighted representation. A new set of partial products is derived and it is shown that all required correction factors can be merged into a single constant one. It is also proposed that part of the correction factor is treated as a partial product, whereas the rest is handled by the final parallel adder. The proposed multipliers utilise a total of (n+1) partial products, each n bits wide and are built using an inverted end-around-carry, carry-save adder tree and a final adder. Area and delay qualitative and quantitative comparisons indicate that the proposed multipliers compare favourably with the earlier solutions
Keywords :
adders; logic design; multiplying circuits; residue number systems; modulo 2n + 1multiplier architecture; parallel adder; weighted representation;
Journal_Title :
Computers & Digital Techniques, IET
DOI :
10.1049/iet-cdt:20060026