Combined topological and functionality-based delay estimation using a layout-driven approach for high-level applications

We discuss the problem of accurate delay estimation of cell-based designs, prior to any physical design tasks. For this purpose, we require accurate wire-length estimates, since wire delays contribute significantly to the overall delay. We present a new technique for wire-length estimation based on a combination of analytical and constructive approaches. Given these wire-length estimates and the cell delays, it is possible to provide worst case delay paths in the design based on the circuit topology. We have also extended our technique to consider false paths, which provides a more accurate functionality based estimate that takes into account the estimated layout information. We validate our technique using the standard MCNC benchmarks. Our results indicate an average 7% accuracy in the worst case delay predictions for designs with up to about 2800 cells