DocumentCode :
1194614
Title :
An edge-based heuristic for Steiner routing
Author :
Borah, Manjit ; Owens, Robert Michael ; Irwin, Mary Jane
Author_Institution :
Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
Volume :
13
Issue :
12
fYear :
1994
fDate :
12/1/1994 12:00:00 AM
Firstpage :
1563
Lastpage :
1568
Abstract :
A new approximation heuristic for finding a rectilinear Steiner tree of a set of nodes is presented. It starts with a rectilinear minimum spanning tree of the nodes and repeatedly connects a node to the nearest point on the rectangular layout of an edge, removing the longest edge of the loop thus formed. A simple implementation of the heuristic using conventional data structures is compared with previously existing algorithms. The performance (i.e., quality of the route produced) of our algorithm is as good as the best reported algorithm, while the running time is an order of magnitude better than that of this best algorithm. It is also shown that the asymptotic time complexity for the algorithm can be improved to O(n log n), where n is the number of points in the set
Keywords :
VLSI; circuit layout CAD; computational complexity; integrated circuit layout; network routing; network topology; printed circuit layout; tree data structures; trees (mathematics); wiring; PCBs; Steiner routing; VLSI; approximation heuristic; asymptotic time complexity; data structures; edge-based heuristic; minimum spanning tree; rectangular layout; rectilinear Steiner tree; running time; wiring area; Capacitance; Costs; Data structures; Integrated circuit interconnections; Joining processes; Printed circuits; Routing; Steiner trees; Very large scale integration; Wires;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/43.331412
Filename :
331412
Link To Document :
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