DocumentCode :
1194975
Title :
A self-aligned short process for insulated-gate bipolar transistors
Author :
Chow, T. Paul ; Baliga, B. Jayant ; Gray, Peter V. ; Adler, Michael S. ; Chang, Michael F. ; Pifer, George C. ; Yilmaz, Hamza
Author_Institution :
General Electric Co., Schenectady, NY, USA
Volume :
39
Issue :
6
fYear :
1992
fDate :
6/1/1992 12:00:00 AM
Firstpage :
1317
Lastpage :
1321
Abstract :
An n-channel vertical insulated-gate bipolar transistor (IGBT) process which implements a self-aligned p+ short inside the DMOS diffusion windows is proposed and demonstrated experimentally. The salient feature of the new process is the placement of a poly-Si plug to define the diffusion window of the p+ short. Similar forward conduction characteristics and tradeoffs with turn-off time were obtained for these self-aligned short IGBTs when compared to conventional IGBTs with non-self-aligned shorts. With a resistive load and no external gate resistor, dynamic latching current was seen to increase with increasing p+ diffusion depth and electron irradiation dosage, as well as with larger p+ diffusion windows
Keywords :
insulated gate bipolar transistors; power transistors; semiconductor technology; DMOS diffusion windows; IGBT; characteristics; diffusion window; dynamic latching current; electron irradiation dosage; forward conduction characteristics; insulated-gate bipolar transistors; n-channel; p+ short; polycrystalline Si plug; resistive load; salient feature; self-aligned short; self-aligned short process; tradeoffs; turn-off time; vertical transistor; Electrons; Geometry; Helium; Insulated gate bipolar transistors; Insulation; Plugs; Power MOSFET; Power electronics; Research and development; Resistors;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/16.137310
Filename :
137310
Link To Document :
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