Analysis and minimization of small-geometry effects on the current gain of self-aligned `etched-polysilicon´ emitter bipolar transistors

The authors report on a detailed analysis of small-geometry effects on the current gain of advanced self-aligned etched-polysilicon emitter bipolar transistors. By studying the dependence of collector and base currents on device geometry and process parameters, they have been able to identify the critical fabrication steps and physical mechanisms involved. The narrow emitter effect is caused by the butting of the emitter-base junction to the field oxide, and is mainly controlled by the gate oxide removal step prior to polysilicon deposition. Short emitter effects are associated with phenomena taking place in the spacer region of the device perimeter during polysilicon patterning, spacer pedestal thermal oxidation, link base implantation, and final rapid thermal anneal. Proper adjustment of all process parameters is shown to allow good control of the narrow-emitter effect and complete compensation of short-emitter effects, showing promise for the future of this CMOS-compatible bipolar transistor structure