Accurate delay models for digital BiCMOS

Author

Raje, Prasad A. ; Saraswat, Krishna C. ; Cham, Kit M.

Author_Institution

Center for Integrated Syst., Stanford Univ., CA, USA

Volume

39

Issue

6

fYear

1992

fDate

6/1/1992 12:00:00 AM

Firstpage

1456

Lastpage

1464

Abstract

A detailed transient analysis of the MOSFET-BJT combination prevalent in digital BiCMOS gates is presented. The analysis accounts for high-level injection leading to BJT β roll-off, base pushout leading to BJT f_T roll-off, short-channel behavior of the MOS drain current, and parasitic capacitances at the base and output. Based on the transient analysis, a piecewise delay expression is derived that shows excellent agreement with measured gate delay and with SPICE simulated delay. The comparisons are made for a wide range of circuit parameters in the gate, namely, MOSFET/BJT size, load capacitance, and supply voltage for both 1- and 0.6-μm BiCMOS technologies. The model is used to optimally size gates, and to determine circuit and device design guidelines to minimize the delay degradation at reduced supply

Keywords

BIMOS integrated circuits; circuit analysis computing; delays; logic gates; transient response; MOS drain current; MOSFET; SPICE simulated delay; base pushout; delay models; digital BiCMOS gates; gate delay; high-level injection; parasitic capacitances; piecewise delay expression; short-channel behavior; transient analysis; Analytical models; BiCMOS integrated circuits; Circuit simulation; Delay; Guidelines; MOSFET circuits; Parasitic capacitance; SPICE; Transient analysis; Voltage;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.137326

Filename

137326