Gate Circuit Layout Optimization of Power Module Regarding Transient Current Imbalance

The layout of power multichip modules is one of the key points of a module design, especially for high power densities, where couplings are enlarged. This paper focuses on dynamic current imbalance between paralleled chips. It can be principally attributed to gate circuit dissymmetry, which modifies inductances and coupling, especially with the power circuit. This paper describes the analysis of an existing power module. An optimization process based on a modification of the gate circuit geometry allows balancing current during switching phases. This approach will be validated with experimental measurements and applied on an existing module