Charge redistribution and noise margins in domino CMOS logic

Domino CMOS gates suffer from an inherent noise margin problem as a result of charge redistribution between parasitic capacitances at internal nodes of the circuit under specific input conditions. This charge redistribution effect can destroy the noise margin and cause glitches at the output of a domino gate. This paper deals with circuit and layout techniques which can help in alleviating the problem. A simple analytical noise margin model for domino gates is discussed. The model is useful to monitor the noise margins of a domino gate while dimensioning the devices in the gate to obtain a specified gate delay. A new technique which allows the design of domino gates with a very large fan-in (typically 20 or more inputs), while maintaining good noise margins and acceptable gate delays, is presented. This technique is useful in, for example, decoder circuits.