Voltage-mode CMOS chaos generator and observation of internal states with a bitmap memory

Author

Takakubo, Hajime ; Takakubo, Kawori ; Mangaser, Ramon A. ; Shono, Katsufusa

Author_Institution

Fac. of Sci. & Technol., Sophia Univ., Tokyo, Japan

Volume

41

Issue

11

fYear

1994

fDate

11/1/1994 12:00:00 AM

Firstpage

759

Lastpage

762

Abstract

A feedback circuit consisting of a three-stage array of weighted CMOS inverters, two CMOS transmission gates and a holding capacitance generates chaos. Trajectories can be designed from the transfer characteristics of the three-stage array of weighted CMOS inverters, which directly produces a nonlinear mapping function. The chaotic trajectories were observed via a bitmap display

Keywords

CMOS digital integrated circuits; bifurcation; bit-mapped graphics; chaos; circuit feedback; signal generators; CMOS transmission gates; bitmap display; bitmap memory; chaotic trajectories; feedback circuit; holding capacitance; internal states observation; nonlinear mapping function; three-stage array; transfer characteristics; voltage-mode CMOS chaos generator; weighted CMOS inverters; CMOS memory circuits; Capacitance; Chaos; Displays; Feedback circuits; Inverters; MOSFETs; Random access memory; Very large scale integration; Voltage;

fLanguage

English

Journal_Title

Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on

Publisher

ieee

ISSN

1057-7122

Type

jour

DOI

10.1109/81.331532

Filename

331532