DocumentCode :
1195380
Title :
A New Simplified Multilevel Inverter Topology for DC–AC Conversion
Author :
Ceglia, Gerardo ; Guzmán, Víctor ; Sánchez, Carlos ; Ibáñez, Fernando ; Walter, Julio ; Giménez, María I.
Author_Institution :
Univ. Simon Bolivar, Caracas
Volume :
21
Issue :
5
fYear :
2006
Firstpage :
1311
Lastpage :
1319
Abstract :
Multilevel converters offer high power capability, associated with lower output harmonics and lower commutation losses. Their main disadvantage is their complexity, requiring a great number of power devices and passive components, and a rather complex control circuitry. This work reports a new multilevel inverter topology using an H-bridge output stage with a bidirectional auxiliary switch. The new topology produces a significant reduction in the number of power devices and capacitors required to implement a multilevel output. The new topology is used in the design of a five-level inverter; only five controlled switches, eight diodes, and two capacitors are required to implement the five-level inverter using the proposed topology. The new topology achieves a 37.5% reduction in the number of main power switches required (five in the new against eight in any of the other three configurations) and uses no more diodes or capacitors that the second best topology in the literature, the Asymmetric Cascade configuration. Additionally, the dedicated modulator circuit required for multilevel inverter operation is implemented using a FPGA circuit, reducing overall system cost and complexity. Theoretical predictions are validated using simulation in SPICE, and satisfactory circuit operation is proved with experimental tests performed on a laboratory prototype
Keywords :
DC-AC power convertors; SPICE; bridge circuits; field programmable gate arrays; invertors; network topology; power capacitors; switching convertors; DC-AC conversion; FPGA circuit; H-bridge output stage; SPICE; asymmetric cascade configuration; bidirectional auxiliary switch; commutation losses; complex control circuitry; cost reduction; modulator circuit; multilevel inverter topology; passive components; power devices; Circuit testing; Circuit topology; Costs; Diodes; Field programmable gate arrays; Inverters; Power capacitors; Power system harmonics; Predictive models; Switches; Capacitor clamped; H-bridge; diode clamped; field programmable gate array (FPGA); multilevel inverter;
fLanguage :
English
Journal_Title :
Power Electronics, IEEE Transactions on
Publisher :
ieee
ISSN :
0885-8993
Type :
jour
DOI :
10.1109/TPEL.2006.880303
Filename :
1687980
Link To Document :
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