A compact gate-level energy and delay model of dynamic CMOS gates

We present an accurate model to estimate the energy and delay of domino CMOS gates derived from a detailed description of internal capacitance switching and discharging currents. The delay dependence with the position of the switching transistor in the gate is accurately described with the advantage that it does not include additional empirical parameters, thus providing the propagation delay in terms of foundry-provided MOSFET parameters. Results show a very high accuracy with a relative error lower than a 3% with respect to HSPICE for a 0.18-μm CMOS technology providing up to three orders of magnitude of speed improvement. The analytical nature of the model makes it suitable for circuit optimization and is the basis for a quick estimation of ULSI circuits power and delay when used in circuit simulation tools.