DocumentCode
1196087
Title
An efficient technique to improve NORA CMOS testing
Author
Ling, Nam ; Bayoumi, Magdy A.
Volume
34
Issue
12
fYear
1987
fDate
12/1/1987 12:00:00 AM
Firstpage
1609
Lastpage
1611
Abstract
This paper presents a novel circuit technique to improve the testability of NORA (NO RAce) CMOS circuits. It is based on the structure, properties and operations of NORA CMOS. The precharge and evaluation properties of NORA CMOS enable one to design simple testing circuit for output stuck-at-zero, stuck-at-one, stuck-open and stuck-on faults. Area and time considerations, as well as the applications of this testability enhancement technique are also discussed.
Keywords
CMOS integrated circuits; Integrated circuit testing; Logic circuit fault diagnosis; CMOS technology; Circuit testing; Clocks; Digital filters; Equations; Finite impulse response filter; Lattices; Linear predictive coding; Notice of Violation; System testing;
fLanguage
English
Journal_Title
Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0098-4094
Type
jour
DOI
10.1109/TCS.1987.1086072
Filename
1086072
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