Minimal area design of power/ground nets having graph topologies

This paper deals with one aspect of routing power and ground nets in integrated circuits composed of modules, where the nets are routed in the channels between the modules. Constraints are assumed on allowable voltage drops for maintaining proper logic levels and switching speed. A procedure for determining the width of routes in power and ground multi-pad distribution systems having graph topologies is presented, where the objective is to minimize the area of the power and ground routes subject to several constraints, such as IR voltage drop and metal migration.