Title :
Equivalent Dominant Pole Approximation of Capacitively loaded VLSI Interconnection
fDate :
2/1/1987 12:00:00 AM
Abstract :
The equivalent dominant pole approximation including delay term is proposed for the transient response calculation of an uniformly distributed URC line loaded with capacitance. Transfer functions for voltage and current excitations have been derived and their applications for modeling of VLSI interconnections have been discussed.
Keywords :
Distributed-parameter circuits, RC; Integrated circuit interconnections; Interconnections, Integrated circuits; Poles and zeros, linear systems; VLSI; Very large-scale integration (VLSI); Circuits; Data communication; Graph theory; Interpolation; Mathematics; Sampling methods; Signal analysis; Tree graphs; Very large scale integration; Wave functions;
Journal_Title :
Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCS.1987.1086108
