Circuit Techniques for CMOS Divide-By-Four Frequency Divider

Author

Jang, S.-L. ; Chuang, Y.-H. ; Lee, S.-H. ; Chao, J.-J.

Author_Institution

Dept. of Electron. Eng., Nat. Taiwan Univ. of Sci. & Technol., Taipei

Volume

17

Issue

3

fYear

2007

fDate

3/1/2007 12:00:00 AM

Firstpage

217

Lastpage

219

Abstract

This letter describes circuit techniques for obtaining divide-by-four (divide4) frequency dividers (FDs) from CMOS ring-oscillator based injection locked frequency dividers (ILFDs). The circuit is made of a two-stage differential CMOS ring oscillator and is based on MOS switches directly coupled to the differential outputs of the ring oscillator. At the supply voltage of 1.8V and at the incident power of 0dBm, for a dual-band ILFD, the divide4 ILFD can provide a locking range of 6.3% from 5.39 to 6.12GHz at low band and 5.9% from 8.84 to 9.38GHz at high band when the dc bias of MOS switches V_inj changes from 0.7 to 1.1V

Keywords

CMOS integrated circuits; MMIC oscillators; frequency dividers; injection locked oscillators; 1.8 V; 5.39 to 6.12 GHz; 8.84 to 9.38 GHz; CMOS ring-oscillator; MOS switches; circuit techniques; divide-by-four frequency divider; dual-band injection locked frequency dividers; CMOS technology; Chaos; Circuit topology; Coupling circuits; Frequency conversion; Ring oscillators; Signal generators; Switches; Switching circuits; Voltage-controlled oscillators; CMOS; direct injection-locked divide-by-four ($div$4) frequency divider (ILFD); nonlinearity; ring oscillator;

fLanguage

English

Journal_Title

Microwave and Wireless Components Letters, IEEE

Publisher

ieee

ISSN

1531-1309

Type

jour

DOI

10.1109/LMWC.2006.890491

Filename

4118206