Title :
Design guidelines for reversed nested Miller compensation in three-stage amplifiers
Author :
Mita, Rosario ; Palumbo, Gaetano ; Pennisi, Salvatore
Author_Institution :
Dipt. Elettrico Elettronico e Sistemistico, Univ. di Catania, Italy
fDate :
5/1/2003 12:00:00 AM
Abstract :
The reversed nested Miller compensation technique applied to a three-stage operational amplifier is discussed in this paper and new and simple design equations, accurately predicting the loop-gain phase margin, are developed. Techniques for parasitic positive-zero cancellation are also investigated and compared. For this purpose, we found that using ing resistors is unpractical. Instead, exploiting only one follower (either a voltage or a current one) in the compensation branch results to be more appropriate. Indeed, not only does it avoid any additional constraint on stage transconductance, but it also overcomes the inherent limitations incurred by voltage and current followers when used to compensate two-stage amplifiers. Post-layout simulations on a CMOS opamp using the parameters of a 0.35-μm process are found to be in good agreement with the expected results.
Keywords :
CMOS analogue integrated circuits; circuit simulation; compensation; integrated circuit design; operational amplifiers; poles and zeros; 0.35 micron; CMOS opamp; current follower; design equations; design guidelines; frequency compensation; loop-gain phase margin; parasitic positive-zero cancellation; post-layout simulations; reversed nested Miller compensation; three-stage operational amplifier; voltage follower; Band pass filters; CMOS process; Circuit optimization; Circuits and systems; Frequency; Guidelines; Matched filters; Solid state circuits; Tuning; Voltage;
Journal_Title :
Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on
DOI :
10.1109/TCSII.2003.811437