• DocumentCode
    1196771
  • Title

    Delay-time sensitivity in linear RC tree

  • Author

    Jain, Navneet K. ; Prasad, V.C. ; Bhattacharyya, A.B.

  • Volume
    34
  • Issue
    4
  • fYear
    1987
  • fDate
    4/1/1987 12:00:00 AM
  • Firstpage
    443
  • Lastpage
    445
  • Abstract
    The study of RC networks is important to understand digital MOS integrated circuits. Several authors studied these networks from the point of view of bounds on voltage waveform [1], [2], signal delay [3], etc. Wyatt [4] developed a qualitative theory of RC meshes having monotone elements. He showed that for a monotone exitation u(t) , the sensitivity of the output node voltage of a nonleaky line is monotonic due to any conductance on the line.
  • Keywords
    Delay effects; RC circuits; Trees; Circuit theory; Delay lines; Distortion measurement; Frequency; Harmonic distortion; Limit-cycles; Nonlinear distortion; Operational amplifiers; Testing; Zinc;
  • fLanguage
    English
  • Journal_Title
    Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0098-4094
  • Type

    jour

  • DOI
    10.1109/TCS.1987.1086143
  • Filename
    1086143
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1196771