• DocumentCode
    1197029
  • Title

    A hierarchical test pattern generation system based on high-level primitives

  • Author

    Sarfert, Thomas M. ; Markgraf, Remo G. ; Schulz, Michael H. ; Trischler, Erwin

  • Author_Institution
    Siemens Nixdorf Informationssyst. AG, Munich, Germany
  • Volume
    11
  • Issue
    1
  • fYear
    1992
  • fDate
    1/1/1992 12:00:00 AM
  • Firstpage
    34
  • Lastpage
    44
  • Abstract
    The authors present an extension of the automatic test pattern generation system SOCRATES to a hierarchical test pattern generation system for combinational and scan-based circuits. The proposed system is based on predefined high-level primitives, e.g., multiplexers and adders. The exploitation of high-level primitives leads to significant improvements in implication, unique sensitization, and multiple backtrace, all of which play a key role in the efficiency of any automatic test pattern generation (ATG) system. In order to perform deterministic ATG and fault simulation for internal faults of high-level primitives, the high-level primitives are dynamically expanded to their gate-level realization. A number of experimental results, achieved on circuits with several tens of thousands of primitives, demonstrate the efficiency of the proposed approach in terms of CPU time, fault coverage, and memory requirements
  • Keywords
    automatic testing; combinatorial circuits; fault location; logic testing; CPU time; SOCRATES; adders; automatic test pattern generation; fault coverage; fault simulation; gate-level realization; hierarchical test pattern generation; high-level primitives; implication; memory requirements; multiple backtrace; multiplexers; predefined high-level primitives; scan-based circuits; unique sensitization; Adders; Automatic test pattern generation; Central Processing Unit; Circuit faults; Circuit testing; Design methodology; Logic arrays; Multiplexing; Test pattern generators; Very large scale integration;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.108617
  • Filename
    108617