Reconciliation of different gate-voltage dependencies of 1/f noise in n-MOS and p-MOS transistors

We have examined the 1/f noise of 3 μm×16 μm, n- and p-MOS transistors as a function of frequency (f), gate-voltage (V_g ) and temperature (T). Measurements were performed for 3 Hz⩽f⩽50 kHz, 100 mV⩽|V_g-V_th|⩽4 V, and 77 K⩽T⩽300 K, where V_th is the threshold voltage. Devices were operated in strong inversion in their linear regimes. At room temperature we find that, for n-MOS transistors, S(V_d)∝V_d²/(V_g-V_th )², and for p-MOS transistors, we generally find that S(V_d)∝V_d²/(V_g-V_th , consistent with trends reported by others. At lower temperatures, however, the results can be very different. In fact, we find that the temperature dependence of the noise and the gate-voltage dependence of the noise show similar features, consistent with the idea that the noise at a given T and V_g is determined by the trap density, D_t(E), at trap energies E=E(T,V_g). Both the T- and V_g-dependencies of the noise imply that D_t (E) tends to be constant near the silicon conduction band edge, but increases as E approaches the valence band edge. It is evidently these differences in D_t(E) that lead to differences in the gate-voltage dependence of the noise commonly observed at room temperature for n- and p-MOS transistors