A Methodology for Drop Performance Modeling and Application for Design Optimization of Chip-Scale Packages

As handheld electronic products are more prone to being dropped during useful life, package-to-board interconnect reliability has become a major concern for these products. This has prompted the industry to evaluate the drop performance of chip-scale packages (CSPs) while mounted on printed wiring boards using board-level drop testing. Although a new board-level test method has been standardized through JEDEC (JESD22-B111), characterization tests take quite a long time to complete, extending the design cycle. This paper proposes a method to compare and evaluate the drop performance through simulations at the design stage. A global-local approach is used to first determine the dynamic response of the board during drop and then to translate it into stresses and strain energy density in solder joints and intermetallic layers. The dynamic response of the board is validated by using data from actual board level testing as per JEDEC standard. The solder joint and intermetallic stresses are then related to drop to failure test data to derive a relative prediction model. The method is then applied to quantify the effect of package design parameters on the drop performance. Factors considered include moldcap thickness, ball pad opening, and land grid array (LGA) versus ball grid array (BGA). The same factors were tested in board level drop to further validate the prediction model. The results indicate that the drop performance can be increased by a factor of 2 or more by changing package design variables