Polyphase IIR decimation filter design for oversampled A/D converters with approximately linear phase

The authors describe a polyphase IIR decimation filter design methodology for oversampled A/D converters by formulating a general nonlinear programming problem that optimizes magnitude response under certain phase linearity constraints. It provides the flexibility of maximizing the signal-to-noise (SNR) when quantization noise with an arbitrary spectral density is presented. A numerical method, the samples-sum-estimation (SSE) method, is introduced to simplify the objective function. Examples show that the proposed design enjoys at least a factor of two reduction in the multiplication rate when compared with conventional FIR filters. This implementation becomes more attractive for applications in modulators with multibit output such as the MASH modulator as well as Σ-Δ modulators with a multibit internal quantizer. The proposed design achieves a SNR of less than 1 dB from that obtained with an ideal low-pass filter at different decimation ratios while the group delay displays an approximately constant value