Optimizing the stage resolution in pipelined, multistage, analog-to-digital converters for video-rate applications

Author

Lewis, Stephen H.

Author_Institution

Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA

Volume

39

Issue

8

fYear

1992

fDate

8/1/1992 12:00:00 AM

Firstpage

516

Lastpage

523

Abstract

The author examines the effect of the stage resolution on some important characteristics of monolithic, pipelined, multistage, analog-to-digital converters (ADCs) with identical stages for video-rate applications. These characteristics are the linearity, speed, area, and power dissipation. It is found that although large stage resolution is desirable from a linearity standpoint, the effect of stage resolution on linearity is small if the ADC uses redundancy and digital correction and if the magnitude of the interstage gain is at least two. Also, minimizing the stage resolution maximizes the conversion rate and minimizes both the die area and the power dissipation

Keywords

analogue-digital conversion; monolithic integrated circuits; pipeline processing; video signals; ADC; conversion rate; die area; digital correction; interstage gain; linearity; monolithic type; pipelined multistage ADC; power dissipation; redundancy; speed; stage resolution; video-rate applications; Analog-digital conversion; CMOS technology; Costs; Digital circuits; Digital signal processing; Integrated circuit technology; Linearity; Pipeline processing; Power dissipation; Signal resolution;

fLanguage

English

Journal_Title

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

1057-7130

Type

jour

DOI

10.1109/82.168943

Filename

168943