Efficient systolic array implementations of IIR digital filtering

Techniques for overcoming the hardware inefficiency in the systolic array implementation of a generic class of IIR digital filters which include the classical direct form digital filter, the Gray-Markel digital lattice or ladder filters, and the Rao-Kailath orthogonal digital filters are discussed. The hardware inefficiency is due to the partial delay transfer and the time rescaling involved in pipelining those filter algorithms. The two schemes proposed improve the hardware efficiency to about 100% with low control overhead