• DocumentCode
    1198744
  • Title

    DFE architectures for high-speed backplane applications

  • Author

    Li, M. ; Wang, S. ; Kwasniewski, T.

  • Author_Institution
    Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada
  • Volume
    41
  • Issue
    20
  • fYear
    2005
  • Firstpage
    1115
  • Lastpage
    1116
  • Abstract
    Embedded and look-ahead decision feedback equalisation (DFE) architectures are proposed to overcome the speed bottleneck of DFE design for high-speed backplane applications. DFE design examples simulated in 0.18 μm CMOS technology demonstrate the feasibility of 10Gbit/s operation over a 34-inch FR4 backplane.
  • Keywords
    CMOS integrated circuits; decision feedback equalisers; 0.18 micron; 10 Gbit/s; CMOS technology; DFE architectures; FR4 backplane; embedded decision feedback equalisation; high-speed backplane application; look-ahead decision feedback equalisation;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:20052206
  • Filename
    1522158
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1198744